`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Westlake University
// Engineer: shenziyang@westlake.edu.cn
// 
// Create Date: 2021/11/20 17:02:22
// Design Name: HW1
// Module Name: BCD_prior_encoder
// Project Name: hw1
// Target Devices: VCU118
// Tool Versions: vivado 2020.1
// Description: Homework 1 for Fudan PLD & HDL courses
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module BCD_prior_encoder(
    input [9:0] swchin          ,//输入10个开关
    output E                    ,//输入有效位记录，若有输入则位0，若无输入则为1
    output [3:0] codeout        //输出的编码
    );
    
    reg [3:0] codeout;
    reg E;
    always @(swchin)
        if (swchin[9] == 0) begin codeout <= 4'b1001; E<= 1'b0; end
        else if (swchin[8] == 0) begin codeout <= 4'b1000; E<= 1'b0; end
        else if (swchin[7] == 0) begin codeout <= 4'b0111; E<= 1'b0; end
        else if (swchin[6] == 0) begin codeout <= 4'b0110; E<= 1'b0; end
        else if (swchin[5] == 0) begin codeout <= 4'b0101; E<= 1'b0; end
        else if (swchin[4] == 0) begin codeout <= 4'b0100; E<= 1'b0; end
        else if (swchin[3] == 0) begin codeout <= 4'b0011; E<= 1'b0; end
        else if (swchin[2] == 0) begin codeout <= 4'b0010; E<= 1'b0; end
        else if (swchin[1] == 0) begin codeout <= 4'b0001; E<= 1'b0; end
        else if (swchin[0] == 0) begin codeout <= 4'b0000; E<= 1'b0; end
        else begin codeout <= 4'b1111; E <= 1'b1; end
endmodule
